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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
FEATURES
* 2 LVPECL outputs * Frequency divide select options: / 1, / 2, /4, /8, /16 * IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML * Output frequency: > 2.5GHz * Output skew: 5ps (typical) * Part-to-part skew: TBD * Additive jitter, RMS: <0.03ps (design target) * Supply voltage range: (LVPECL), 2.375V to 3.465V Supply voltage range: (ECL), -3.465V to -2.375V * -40C to 85C ambient operating temperature * Pin compatible with SY89874U
GENERAL DESCRIPTION
The ICS889874 is a high speed 1:2 Differentialto-LVPECL Buffer/Divider and is a member of HiPerClockSTM the HiPerClockS TM family of high performance clock solutions from ICS. The ICS889874 has a selectable /1, /2, /4, /8, /16 output divider, which allows the device to be used as either a 1:2 fanout buffer or frequency divider. The clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.
ICS
BLOCK DIAGRAM
S2
PIN ASSIGNMENT
VCC S0
Q0 nRESET
Enable FF Enable MUX
1 2 3 4
16 15 14 13 12 11 10 9 5
S2
S1
VEE
IN VT VREF_AC nIN
nQ0 Q1 Q0
0
nQ1
6
nc
7
VCC
8
nRESET
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nQ0
1
IN VT nIN S0
Decoder
Q1 nQ1
00 01 10 11
/2 /4 /8 /16
ICS889874
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
S1
VREF_AC
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Type Description Differential output pair. LVPECL / ECL interface levels. Differential output pair. LVPECL / ECL interface levels. Pullup Select pins. LVCMOS/LVTTL interface levels. No connect. Positive supply pins. Synchronizing enable/disable pin. When LOW, resets the divider. When HIGH, unconnected. Input threshold is VCC/2V. Includes a 37k pull-up resistor. LVTTL / LVCMOS interface levels. Inver ting differential LVPECL clock input. Reference voltage for AC-coupled applications. Termination input. Non-inver ting LVPECL differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 15, 16 6 7, 14 8 9 10 11 12 Name Q0, nQ0 Q1, nQ1 S2, S1, S0 nc VCC nRESET nIN VREF_AC VT IN Output Output Input Unused Power Input Input Output Input Input Pullup
Power Negative supply pin. 13 VEE NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLUP Parameter Input Pullup Resistor Test Conditions Minimum Typical 37 Maximum Units K
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Outputs Q0, Q1 Disabled; LOW nQ0, nQ1 Disabled; HIGH
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs nRESET 0 Selected Source IN, nIN
1 IN, nIN Enabled Enabled NOTE: After nRESET switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
VCC/2
nRESET IN nIN
tRR VIN tPD
nQ Q
VOUT Swing
FIGURE 1. nRESET TIMING DIAGRAM (WHEN S2 = 1)
TABLE 3B. TRUTH TABLE
Inputs nRESET 1 1 1 1 1 S2 0 1 1 1 1 S1 X 0 0 1 1 S0 X 0 1 0 1 Outputs Reference Clock (pass through) Reference Clock /2 Reference Clock /4 Reference Clock /8
Reference Clock /16 Q = LOW, nQ = HIGH 0 1 X X Clock Disable; (NOTE 1) Q = LOW, nQ = HIGH 0 0 X X Clock Disable; (NOTE 1) NOTE 1: Reset/Disable function is asser ted on the next clock input (IN/nIN) high-to-low transition.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
-0.5V to +4.0V -0.5V to VCC + 0.5 V 50mA 100mA 50mA 100mA 0.5mA -65C to 150C 51.5C/W (0 lfpm) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Input Current IN, nIN VT Current, IVT VREF_AC Sink/Source, IVREF_AC Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V10% OR 2.5V5%; TA = -40C TO 85C
Symbol VCC I EE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 50 Maximum 3.63 Units V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V10% OR 2.5V5%; TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current VCC = VIN = 3.63V VCC = 3.63V, VIN = 0V Test Conditions Minimum 2 0 -125 Typical Maximum VCC + 0.3 0.8 20 -300 Units V V A A
TABLE 4C. DC CHARACTERISTICS, VCC = 3.3V10% OR 2.5V5%; TA = -40C TO 85C
Symbol RIN VIH VIL VIN VDIFF_IN IIN VREF_AC Parameter Differential Input Resistance Input High Voltage Input Low Voltage Input Voltage Swing Differential Input Voltage Swing Input Current Bias Voltage (IN, nIN) VCC - 1.35 (IN, nIN) (IN, nIN) (IN, nIN) 1.2 0 0.15 0.3 45 Test Conditions Minimum Typical 10 0 VCC VCC - 0.15 2.8 Maximum Units V V V V mA V
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Conditions Minimum Typical VCC - 1.005 VCC - 1.78 800 1.60 Maximum Units mV mV mV V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V10% OR 2.5V5%; TA = -40C TO 85C
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Voltage Swing Differential Output Voltage Swing
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V10% OR 2.5V5%; TA = -40C TO 85C
Symbol fMAX Parameter Maximum Output Frequency Maximum Input Frequency Propagation Delay, (Differential); NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Reset Recover y Time Output Rise/Fall Time Clock Enable Setup Time Clock Enable Hold Time EN to IN, nIN EN to IN, nIN 20% to 80% Condition Output Swing 450mV / 2, /4, /8, /16 Input Swing: < 400mV Input Swing: 400mV Minimum 2 2 725 725 5 TBD <0.03 TBD 180 TBD TBD Typical Maximum Units GHz GHz ps ps ps ps ps ps ps ps ps
t PD tsk(o) tsk(pp) tjit
tRR tR/tF tS tH
All parameters characterized at 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
VCC
Qx
SCOPE
nIN
LVPECL
nQx
VEE V EE IN
V
IN
Cross Points
V
IH
V
IL
-0.375V to -1.63V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nIN
80% Clock Outputs
80% VSW I N G
IN nQ0, nQ1 Q0, Q1
tPD
20% tR tF
20%
OUTPUT RISE/FALL TIME
nIN IN
PROPAGATION DELAY
VIN, VOUT
VDIFF_IN, VDIFF_OUT 1600mV (typical)
nRESET
t HOLD
t SET-UP
800mV (typical)
SETUP & HOLD TIME
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SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1 250
Zo = 50 Ohm
R3 250
+
+
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL Driv er
2,5V LVPECL Driv er
R1 50
R2 50
R2 62.5
R4 62.5
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
BUILT-IN 50 TERMINATIONS INTERFACE
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
2.5V LVPECL INPUT
WITH
The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both V SWING and V OH must meet the V PP and V CMR input requirements.Figures 4A to 4D show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven
3.3V or 2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm
IN
Zo = 50 Ohm
IN
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
VT nIN
VT nIN
Receiver With Built-In 50 Ohm
2.5V LVPECL
R1 18
Receiver With Built-In 50 Ohm
FIGURE 4A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
FIGURE 4B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm
IN
Zo = 50 Ohm
IN
Zo = 50 Ohm
VT nIN
Zo = 50 Ohm
VT nIN
CML - Open Collector
Receiver With Built-In 50 Ohm
CML - Built-in 50 Ohm Pull-up
Receiver With Built-In 50 Ohm
FIGURE 4C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm R2 25 VT nIN
2.5V
SSTL
Receiver With Built-In 50
FIGURE 4E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
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REV. A MAY 19, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
BUILT-IN 50 TERMINATIONS INTERFACE
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V LVPECL INPUT
WITH
The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
IN
Zo = 50 Ohm
Zo = 50 Ohm
IN
Zo = 50 Ohm
VT nIN
VT nIN
LVDS
Receiver With Built-In 50 Ohm
LVPECL
R1 50
Receiver With Built-In 50 Ohm
FIGURE 5A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
FIGURE 5B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
IN
Zo = 50 Ohm
IN
Zo = 50 Ohm
Zo = 50 Ohm
VT nIN
VT nIN
CML- Open Collector
Receiver With Built-In 50 Ohm
CML- Built-in 50 Ohm Pull-Up
Receiver With Built-In 50 Ohm
FIGURE 5C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH OPEN COLLECTOR
FIGURE 5D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
3.3V
3.3V
R1
25
Zo = 50 Ohm
IN
Zo = 50 Ohm
VT nIN
SSTL
R2
25
Receiver With Built-In 50 Ohm
FIGURE 5E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
BUILT-IN 50 TERMINATION UNUSED INPUT HANDLING
3.3V DIFFERENTIAL INPUT
WITH
To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 6.
3.3V
3.3V
R1 1K
IN VT nIN
R2 1K
Receiver with Built-In 50 Ohm
FIGURE 6. UNUSED INPUT HANDLING
2.5V DIFFERENTIAL INPUT
WITH
BUILT-IN 50 TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 7.
2.5V
2.5V
R1 680
IN VT nIN
R2 680
Receiver with Built-In 50 Ohm
FIGURE 7. UNUSED INPUT HANDLING
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
16 LEAD VFQFN
JA 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
51.5C/W
TRANSISTOR COUNT
The transistor count for ICS889874 is: 326
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
16 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS889874
1:2 DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER
Marking 874A 874A Package 16 Lead VFQFN 16 Lead VFQFN on Tape and Reel Count 120 per tube 3500 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS889874AK ICS889874AKT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 889874AK
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